1. Technical Field
Embodiments of the invention generally relate to the field of integrated circuits and more particularly, but not exclusively, to write operations performed at a dynamic random access memory device.
2. Background Art
Modern Dynamic Random Access Memory (DRAM) designs are facing process yield issues that require internal error correction mechanisms such as Error Correction Code(s) (ECC). Current solutions for DRAM devices, such as a Joint Electron Device Engineering Council (JEDEC) Wide input-output 2 (WIO2) compliant DRAM device and a JEDEC Low Power Dual Data Rate 4 (LPDDR4) compliant DRAM device, internally perform single error correction (SEC) using 136/128 Hamming codes, where 8 dedicated bits per 128 data bits are used for coding. External data transfer size and internal prefetch size are both 128-bits in the cases of WIO2 and LPDDR4 compliant DRAM devices.